Computer Engineering, UW–Madison

From GaN gate drives to RISC‑V pipelines.

I design fast gate-drive hardware in a wide-bandgap research lab, and I build digital systems in Verilog and SystemVerilog.

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Summer 2027
Senior Technical Intern, power electronics, Leonardo DRS
Fall 2027
Starting an MS focused on ASIC/FPGA design
Double-pulse test Run
  • 1VGS 5 V/div
  • 2VDS 250 V/div
  • 3ID 10 A/div
  • 2 µs/div

Bus 500 V, peak current 25 A

Modeled waveform, not measured data. Move across the screen to read values.

About

I'm finishing a BS in Computer Engineering at UW–Madison in summer 2027 and starting an MS that fall, focused on ASIC/FPGA design. In summer 2027 I'll join Leonardo DRS as a Senior Technical Intern in power electronics.

My work sits on both sides of the gate. In Prof. Chirag Gupta's Wide-Bandgap Materials and Devices Lab I design optically isolated gate drives and laser drivers for GaN devices. In coursework I've built a pipelined RISC-V processor, FPGA robot control in SystemVerilog, and Linux kernel system calls. I also design and assemble PCBs for Badger Solar Racing's Low Voltage team.

Dean's Honor List every semester. Two-time Claude and Dora Richardson Scholarship recipient.

Research

Ongoing undergraduate research in the Wide-Bandgap Materials and Devices Lab with Prof. Chirag Gupta: switching GaN transistors with light instead of a driver IC.

Optical double-pulse test setup with fiber-coupled laser modules and chip-on-board GaN gate drive
Lab bench with an enclosed double-pulse test fixture, two oscilloscopes showing the two pulses, and bench supplies
Double-pulse test bench
Ryan Pfeifer with Parameswaran Ramanathan, ECE Interim Department Chair, at the SPARK poster symposium
With Parameswaran Ramanathan, ECE Interim Department Chair

Optically isolated GaN gate drive

Undergraduate Researcher, Wide-Bandgap Materials and Devices Lab

A discrete, chip-on-board gate drive that switches bare-die GaN HEMTs through optical fiber, targeting sub-10 ns VDS transitions with full galvanic isolation. I modeled GaAs phototransistor switching in LTspice, laid out the chip-on-board PCBs in Altium to minimize parasitic inductance, and evaluated switching speed with custom-packaged bare-die parts in a double-pulse test.

I presented this work at the 2026 ECE SPARK poster symposium and received the Complex Concepts Communicator Award, one of three awards across 31 presenters, for clarity in explaining the research to peers and faculty.

  • <10 nstarget VDS transition
  • 0.5–2 nHparasitics included in SPICE
  • 1 of 3awards, 31 presenters
  • LTspice
  • Altium Designer
  • GaN HEMTs
  • Chip-on-board PCB
  • Double-pulse test

View the SPARK poster (PDF)

Single voltage bus Step-down power board Current source 1 0.2–2.5 A Current source 2 0.2–2.5 A Current source 3 0.2–2.5 A

Three-channel tunable GaN laser driver

Undergraduate Researcher, Wide-Bandgap Materials and Devices Lab

A 4-layer Altium board, paired with a step-down power board, that sets 0.2–2.5 A per channel from a single voltage bus. It removed three external current generators and six input ports from the test setup, and it replicated prior results on a far smaller board than the off-the-shelf EPC drivers it replaced.

  • 0.2–2.5 Aper channel, tunable
  • 3 fewerexternal current generators
  • 6 fewerinput ports
  • Altium Designer
  • 4-layer PCB
LED board, two hyper-red LEDs ≈ 8 mm PV cell Gate-drive rail + C Phototransistor totem pole GaN FET

Optically powered GaN gate drive In progress

Undergraduate Researcher, Wide-Bandgap Materials and Devices Lab

The next step removes the electrical supply from the gate side entirely. A sandwich PCB holds two OSRAM hyper-red LEDs about 8 mm above an ANYSOLAR SM500K12L PV cell. The PV cell, with parallel capacitance, supplies the gate-drive rail, and a totem pole of custom PAAS phototransistors drives the gate of an Innoscience INN650N080BS bare-die GaN FET.

  • Altium Designer
  • Optical power delivery
  • Bare-die GaN
  • Sandwich PCB

Projects

Digital design, boards that had to survive a car, and systems code.

Pipelined RISC-V CPU

Academic project, team of three

A 5-stage pipelined RV32I processor in Verilog. Data hazards are handled with EX/MEM and MEM/WB forwarding plus a one-cycle stall on load-use. Branches are predicted not taken and resolved in EX, with a pipeline flush on redirect.

  • Verilog
  • RV32I
  • Data forwarding
  • Hazard detection
  • Branch prediction

View the datapath schematic (PDF)

Step through the pipeline. This model follows the same forwarding, stall and flush rules as the RTL.

Cycle 1
IFFetch
IDDecode
EXExecute
MEMMemory
WBWriteback

      3D render of the redesigned lighting control board PCB in Altium Designer
      Badger Solar Racing team members around the solar car on a track
      Badger Solar Racing's car at the track

      Solar Racing: lighting control board

      Low Voltage Team Member, Badger Solar Racing

      Problem
      6 of 7 first-build boards failed when the 12 V header shorted to the adjacent 5 V test header.
      Fix
      I separated the headers and added an eFuse and overvoltage protection in the Altium redesign, then hand-assembled and soldered the new boards.
      Result
      The redesign ran failure-free through several full-vehicle trial assemblies and passed the road safety check.

      I also worked with the firmware team on the CAN protocol that links the board to the rest of the car.

      • Altium Designer
      • eFuse and OVP
      • CAN bus
      • PCB assembly

      Badger Solar Racing

      MazeRunner

      Academic project

      An autonomous robot that navigates a prebuilt physical maze, fusing gyroscope and IR sensor data to calculate heading and wall distance for PID motor control. Logic was verified in ModelSim and synthesized to an FPGA with Synopsys Design Compiler.

      • SystemVerilog
      • ModelSim
      • FPGA
      • PID control

      View on GitHub

      User space Calling process buffer Target process address space Kernel Custom system calls read / write process memory syscall copy

      Linux kernel syscalls for cross-process memory

      Academic project, CS 537 Operating Systems

      Custom Linux kernel system calls that let one process read and write another process's memory.

      • C
      • Linux kernel
      • System calls
      • Virtual memory

      Source is private per university course policy. Happy to walk through the code directly.

      Battleship

      Academic project

      A full two-player implementation of Battleship in C using FreeRTOS on an Infineon microcontroller. Built joystick- and IMU-driven controls for board navigation, drove an LCD display and I/O-expander-based LED indicators over SPI and I2C, and handled real-time interboard synchronization over UART for the two-player game state.

      • C
      • FreeRTOS
      • SPI
      • I2C
      • UART

      Source is private per university course policy. Happy to walk through the code directly.

      Skills

      Languages and RTL
      SystemVerilog, Verilog, C, Java, MATLAB, Git, Linux/Unix
      EDA and simulation
      Altium Designer, LTspice, ModelSim, Synopsys Design Compiler, Cadence, Quartus
      Protocols and embedded
      SPI, I2C, UART, CAN bus, FreeRTOS
      Lab and bench
      Oscilloscopes, double-pulse testing, PCB assembly and soldering

      Contact

      The fastest way to reach me is email.

      ryan.pfeifer@wisc.edu

      LinkedIn GitHub Resume (PDF)